IEEE Std 1800 System Verilog - Unified Hardware Design, Specification, and Verification Language

Text Registration

IEEE Std 1800 System Verilog - Unified Hardware Design, Specification, and Verification Language

Status

Published

on 26 Jan 2012

Year of Creation

2011

IEEE

Registration Number

TX0007497702

on 26 Jan 2012

The U.S. Copyright record (Registration Number: TX0007497702) dated 26 Jan 2012, pertains to an electronic file (eService) titled "IEEE Std 1800 System Verilog - Unified Hardware Design, Specification, and Verification Language" created in 2011. The copyright holder is IEEE, known for their creative contributions in text registration. For any inquiries concerning this copyrighted material, kindly reach out to IEEE.

IEEE

Application Details

Registration Number

TX0007497702

Registration Date

1/26/2012

Year of Creation

2011

Agency Marc Code

DLC-CO

Record Status

New

Corporate Author

IEEE

Physical Description

Print material, 3 v

First Publication Nation

United States

Corporate Authors

IEEE

Notes

Rights Note: William Hagen, IEEE, 445 Hoes Lane, Piscataway, NJ, 08854, United States, (732) 562-3966, w.hagen@ieee.org

Statements

Application Title Statement: IEEE Std 1800 System Verilog - Unified Hardware Design, Specification, and Verification Language

Author Statement: IEEE employer for hire Domicile: United States Authorship: Collective Work

Notes

Rights Note: William Hagen, IEEE, 445 Hoes Lane, Piscataway, NJ, 08854, United States, (732) 562-3966, w.hagen@ieee.org

Statements

Application Title Statement: IEEE Std 1800 System Verilog - Unified Hardware Design, Specification, and Verification Language

Author Statement: IEEE employer for hire Domicile: United States Authorship: Collective Work

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